View AK2346B_7556776.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

asahi kasei [AK2346B] ms1409-e-00 2012/05 - 1 - AK2346B two-way radio audio processor 1. features ? audio processing ? tx and rx amplifier ? pre/de-emphasis circuit ? compressor and expander with no external components ? scrambler and de-scrambler in frequency inversion type ? limiter with level adjuster ? splatter filter for wide and narrow band ? digital controlled amplifier for microphone, modulator and demodulator sensitivity ? 1200/2400bps msk modem with frame detection ? wide range operation voltage: 1.9v to 5.5v, temperature: -30 to 75 c ? oscillator circuit for 3.6864mhz crystal ? serial control interface operation ? compact plastic packaging, 24-pin ssop 2. description AK2346B includes audio filter, limiter, splatter fi lter, compandor, scrambler, msk modem, which is highly integrated two-way radio baseband functions for frs and lmr. audio high-pass filter shows a high attenuation in magnitude response characteristics under 250hz that supports to eliminate a subaudio tone clearly. tx limiter for deviation control has a limiting le vel adjuster by applying a dc voltage via external components. splatter filter has the magnitude response for narrowband(fc=2.55khz) and wideband(3.0khz) to meet various regulatory agencies in the world wide. compandor is no adjustment type because it in cludes all parametric components inside the chip. scrambler circuit is composed of frequency inve rsion circuit by double balanced mixer that has 3.388khz carrier clock. msk modem for data communication can be chosen either 2400bps or 1200bps. 2400bps data rate provides a high speed data transmission and 1200bps supports a low ber(bit error rate) performance that is suitable for under weak electrical field condition application. there are four signal level adjusters for microphone, modulator and demodulator sensitivity by digital controlled amplifier (volume). ? pin assignment agndin agnd txin txino limlv extlimin mod vss tclk tdata di/o rdf/fd 11 12 1 2 3 4 5 6 7 8 9 10 test rxin rxino rxlpfo rxaf rxafin expout vdd xin xout dir sclk 24 23 22 21 20 19 18 17 16 15 14 13
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 2 - 3. contents 1. feat ures.................................................................................................................... ........... 1 2. descr ipti on................................................................................................................. .......... 1 3. cont ents .................................................................................................................... .......... 2 4. block diagram ............................................................................................................... ...... 3 5. circuit c onfigurat ion ....................................................................................................... ..... 4 6. pin/f unction................................................................................................................ ......... 5 7. absolute ma ximum ratings ................................................................................................. 7 8. recommended operat ing cond itions .................................................................................. 7 9. digital dc c haracteri stics.................................................................................................. ... 7 10. power c onsumption.......................................................................................................... . 8 11. analog char acterist ics..................................................................................................... ... 9 12. level diagr am.............................................................................................................. .... 14 13. serial interfac e configur ation .......................................................................................... 15 14. digital ac ti ming .......................................................................................................... .... 20 15. msk modem descrip tion ............................................................................................... 23 16. recommended external application circuits ................................................................... 26 17. packa ging .................................................................................................................. ...... 30 18. important notice ........................................................................................................... ... 31
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 3 - 4. block diagram com- p resso r pre- emphasis - + txa1 vr4 vr3 rxlpf expan- der msk demodulato r msk modulator msk bpf control register tdata tclk dir sclk di/o rdf/fd + mod - + rxa2 expout rxafin rxaf osc xin xout limiter limlv extlimin de- emphasis rxlpfo agnd + + a gnd a gndin vdd vss power on at mode 1,2,3,4 power on at mode 2,4 power on at mode 3,4 power on at mode 2,3,4 splatter vr2 smf - + rxa1 tx/rx hpf scrambler /de- scrambler vr1 ( hpf ) test 4 3 22 23 21 10 9 14 13 11 12 24 17 8 1 2 15 16 20 19 18 7 5 6 txin txino rxin rxino fc=2.55khz/ 3.0khz fc=300hz -6~+4.5/1.5db -4~+3.5/0.5db -9.2~+3.0/0.2db -18,-4.5~+4.5 /1.5db
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 4 - 5. circuit configuration block description txa1 the operational amplifier for transmit audio gain adjustment and for the filter to eliminate aliasing noise by the scf(switched capacitor filter) in the following stage. please select an external resistor and capacitor to set the gain less than 30db and the cut-off frequency to about 10khz. vr1 (hpf) digitally controlled amplifier (volume) for transm it audio signal level which is adjustable in 1.5db steps over a ?6.0db to +4.5db range by setting vr12 to vr10 register. compressor the circuit to compress transmits audio signal level by 1/2 in db scale. standard cross-point is ?10dbx. tc register sets off/on to the circuit. pre-emphasis the circuit to emphasis the high-frequency component of transmit audio signal to improve s/n ratio of the modulation signal. tx/rxhpf the high-pass filter to eliminate the low-frequency component less than 250hz for transmit and receive audio signal. scrambler/ descrambler scramble/de-scramble circuit to inverse transmit and receive audio spectrum by 3.388khz carrier signal. em and pcont register can set scramble/de-scr amble or emphasis circuit. both circuits do not use simultaneously. limiter an amplitude limiting circuit to suppress the frequency deviation of the modulation signal. the limitation level can be adjusted by applying a dc voltage to the limlv pin. if the limlv pin is open, the limitation level is applied to a predetermined level. splatter the circuit to eliminate the high frequency component higher than 3khz included in the limiter output signal or the msk modulator signal. the cut-off frequency can be selected by spl register. vr2 digitally controlled amplifier (volume) for mod output level which is adjustable in 0.2db steps over a ?3.2db to +3.0db range by setting vr25 to vr20 register. vr25 is a ?6/0db coarse bit. smf the smoothing filter to eliminate the high frequency and clock component caused in scf circuits. rxa1 the operational amplifier for receives audio gain adjustment and for the filter to eliminate aliasing noise by the scf in the following stage. please select an external resistor and capacitor to set the gain less than 20db and the cut-off frequency to about 40khz. vr3 digitally controlled amplifier (volume) for rece ive audio signal level which is adjustable in 0.5db steps over a ?4.0db to +3.5db range by setting vr33 to vr30 register. rxlpf the low-pass filter to eliminate the high frequency component higher than 3khz for receive audio signal. de-emphasis the circuit to de-emphasis the emphasized signal by pre-emphasis circuit. expander the circuit to expand the receive audio signal level to double in db scale compressed by compressor standard cross-point is ?10dbx. tc register sets off/on to the circuit. vr4 digitally controlled amplifier (volume) for expout output level which is adjustable in 1.5db, steps over a ?18db and ?4.5db to +4.5db range by setting vr42 to vr40 register. rxa2 the operational amplifier used on smoothing filter to eliminate clock component included in expout output signal. please set the gain to 0db and the cut-off frequency to about 20khz by external resistor and capacitor. msk modulator the circuit to generate a msk signal according to the received digital data from tdata pin. msk bpf the band-pass filter to eliminate the low and high frequency component for received msk signal. msk demodulator the circuit to reproduce the 1200/2400bps receive clock and data from msk signal at rxin pin.
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 5 - block description agnd the circuit to generate the reference voltage (1/2vdd) for internal analog signal. osc the circuit to oscillate the 3.6864mhz reference clock with an external crystal oscillator and resistor and capacitors. control register the control register controls the status of internal switches and digitally controlled amplifiers of ic by serial data that consists of 3 address bits and 8 data bits. at the start up a power-on-reset circuit works and ?reset? data are set to the control register. (refer to the control register map) the data buffer stores 8 bits of the msk receiv ed data to smooth the signal interface with microprocessor. 6. pin/function package signal pin no name type function 1 agndin i analog ground input pin. connect the capacitor to stabilize the analog ground level. this pin also has reset function for the registers. connecting to the low level, ?reset? data are set to the control register. 2 agnd o analog ground output pin. connect the capacitor to stabilize the analog ground level. 3 txin i transmit audio signal input pin. this is the inverting input pin for txa1. it composes a microphone amplifier with an external resister and capacitor. 4 txino o txa1 feedback output pin. 5 limlv i limit level adjuster pin. a limit level can be adjusted by applying a dc voltage to this pin. if it is open, the level is fixed to a predetermined level. 6 extlimin i external signal input pin pre-limiter circuit. this pin is available for external tone signal. 7 mod o the modulated transmit signal output pin. load impedance larger than 10k : can be drive. 8 vss pwr negative power supply pin. normally supply 0v to this pin. 9 tclk o clock output pin for msk transmission data. setting the register named txsw2 to ?0? puts out 1.2/2.4khz clock. if the register is set to ?1?, it goes to high level. 10 tdata i msk transmission data input pin. data are latched synchronizing with the tclk rising edge. 11 di/o i/o serial data input and output pin. input for register setting data and output for msk receive data. 12 rdf/fd o msk signal received flag and frame detection signal output pin. this pin puts out two types of signal that depends on the status of register named fsl. in case fsl equal ?1?, it is received fl ag mode (rdf). so the pin puts out low level after 8 bits of msk receive signal have been written to the internal register. in case fsl equal ?0?, it is frame detection mode (fd). so the low pulse is put out after a frame pattern is detected.
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 6 - package signal pin no name type function 13 sclk i clock input pin for serial data i/o. 14 dir i serial data i/o control pin. 15 xout i crystal oscillator connecting input pin. 16 xin i/o crystal oscillator connecting input and output pin. to connect a 3.6864mhz crystal oscillator between this pin and xout pin generates the reference clock internally. in case of externally supplied clock operation, connect to this pin. for more information, please refer to external application circuits. 17 vdd pwr positive power supply pin. normally connect to 1.9v to 5.5v noiseless power-supply. also this pin must be decoupled to vss pin by 0.1uf capacitor mounted close to the device pins. 18 expout o expander and vr4 output pin. 19 rxafin i receive audio signal input pin. this is the inverting input of rxa2. it composes a smoothing filter by external resistor and capacitor. 20 rxaf o receive audio signal output pin. this is the output pin of rxa2. load impedance more than 10k : can be driven. 21 rxlpfo o receive lpf output pin. this is a monitor pin for tone signal. 57.6khz sampling-clock is included, so please eliminate this signal component by lpf externally. load impedance more than 10k : can be driven. 22 rxino o rxa1 feedback output pin. 23 rxin i demodulated audio signal input pin. this is the inverting input of rxa1. it composes a pre-filter with external resistor and capacitor. 24 test i test register control input pin. when this pin set to high level, test re gister is controllable . please set to low level or open for normal operation.
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 7 - 7. absolute maximum ratings parameter symbol min. max. units power supply voltage vdd -0.3 6.5 v ground level vss 0 0 v input voltage v in -0.3 vdd+0.3 v input current (except power supply pin) i in -10 +10 ma storage temperature t stg -55 130 c note : all voltages with respect to the vss pin. caution : exceeding these maximum ratings can result in damage to the device. normal operation cannot be guaranteed under this extreme. 8. recommended operating conditions parameter symbol condition min. typ. max. units operating temperature ta -30 75 c power supply voltage vdd 1.9 3.0 5.5 v analog reference voltage agnd 1/2vdd v r l1 mod, rxaf, rxlpfo 10 output load resistance r l2 txino, rxino, expout 30 k c l1 mod, rxaf, rxlpfo 50 output load capacitance c l2 txino, rxino, expout 15 pf master clock frequency f ck xin, xout 3.6864 mhz note : all voltages with respect to the vss pin. 9. digital dc characteristics parameter symbol condition min. typ. max. units v ih1 tdata, di/o 0.7vdd high level input voltage v ih2 sclk, dir 0.8vdd v v il1 tdata, di/o 0.3vdd low level input voltage v il2 sclk, dir 0.2vdd v high level input current i ih v ih =vdd tdata, di/o, sclk, dir 10 ua low level input current i il v il =0v tdata, di/o, sclk, dir -10 ua high level output voltage v oh i oh =+0.2ma tclk, rdf/fd, di/o vdd-0.4 vdd v low level output voltage v ol i ol =-0.4ma tclk, rdf/fd, di/o 0.0 0.4 v
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 8 - 10. power consumption parameter symbol condition min. typ. max. units idd0 mode 0 osc:off, audio: off, modem:off 0.1 0.3 idd1 mode 1 osc:on , audio: off, modem:off 0.9 1.7 idd2 mode 2 osc:on , audio: on , modem:off 5.5 7.6 idd3 mode 3 osc:on , audio: off, modem:on 2.2 3.4 current consumption idd4 mode 4 osc:on , audio: on , modem:on 6.1 8.4 ma
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 9 - 11. analog characteristics for the following conditions unless otherwise spec ified: f=1khz, emphasis: on, compandor: on, scrambler: off, vr1=vr2=vr3=vr4=0db with the external circuit shown in example page.26 to 29. ?dbx? is standardized unit for 1.9v to 5.5v oper ation, 0dbx=-5+20log(vdd/2)dbm, 0dbm=0.775vrms. 1) tx audio system parameter condition min. typ. max. units notes standard input level @txino -10 dbx absolute gain txino to mod -1.5 0 +1.5 db limit level extlimin to mod without external r adjustment with external r adjustment -8.6 -7.6 -6.6 -6.6 dbx compressor linearity txino to mod txino=-44dbx txino=-50dbx relative value to 0db for mod level of -10dbx txino. -20.0 -24.0 -17.0 -20.0 -14.0 -16.0 db compressor distortion txino to mod txino=-10dbx 30khz low-pass filtering -35 db noise level with no signal input txino to mod c-message filtering -36.5 dbm vr1 attenuation error txino to mod -6.0 db to 4.5db, 1.5db/step -1.5 +1.5 db vr2 att error (vr24,23,22,21,20) txino to mod -3.2db to +3.0db, 0.2db/step -0.2 +0.2 db vr2 att error (vr25=0) txino to mod relative error for -6/0db -6.4 -6 -5.6 db 2) rx audio system parameter condition min. typ. max. units notes standard input level @rxino -10 dbx rxino to rxlpfo -1.5 0 +1.5 db absolute gain rxino to rxaf -1.5 0 +1.5 db expander linearity rxino to rxaf rxino=-25dbx rxino=-30dbx relative value to 0db for rxaf level of -10dbx rxino -33.0 -45.0 -30.0 -40.0 -27.0 -35.0 db expander distortion rxino to rxaf rxino=-5dbx 30khz low-pass filtering -35 db noise level with no signal input rxino to rxaf c-message filtering -70 dbm vr3 attenuation error rxin0 to rxaf -4.0db to +3.5db, 0.5db/step -0.5 +0.5 db vr4 attenuation error rxin0 to rxaf -4.5 to +4.5db, 1.5db/step -1.5 +1.5 db vr4 att error (vr42,41,40=0,0,0) rxin0 to rxaf relative error for -18/0db -20 -18 -16 db
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 10 - 3) audio filter characteristics 3.1) emphasis: off , compandor: off, scrambler: off (design target values) parameter condition min. typ. max. units notes 250hz -50 -38 db 300hz to 2.0khz 2.5khz 3.0khz 6.0khz -1.0 -1.5 -4.0 -32 +1.0 +1.0 -1.0 -28 db spl =0 fc=2.55k tx overall characteristics txino to mod relative value to gain at 1khz 300hz to 2.5khz 3.0khz 6.0khz -1.0 -1.5 -26 +1.0 +1.0 -22 db spl =1 fc=3.0k rx overall characteristics rxino to rxaf relative value to gain at 1khz 250hz 300hz 350hz to 3.0khz 6.0khz -1.5 -1.0 -49 -38 -38 +1.0 +1.0 -28 db 3.2) emphasis: on , compandor: off, scrambler: off parameter condition min. typ. max. units notes 250hz -57 -40 db 300hz 2.5khz 3.0khz 6.0khz -12.5 +6.0 +4.5 -23 -9.5 +9.0 +8.5 -18 db spl =0 fc=2.55k tx overall characteristics txino to mod relative value to gain at 1khz 300hz 2.5khz 3.0khz 6.0khz -12.5 +6.0 +7.0 -17 -9.5 +9.0 +10.5 -12 db spl =1 fc=3.0k rx overall characteristics rxino to rxaf relative value to gain at 1khz 250hz 300hz 3.0khz 6.0khz +8.5 -11.5 -38 -52 -26 +11.5 -8.5 -40 db
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 11 - ? audio path frequency response (emphasis:off) figure 1: tx overall re sponse without pre-emphasis. figure 2: rx overall re sponse without de-emphasis. -60 -50 -40 -30 -20 -10 0 10 20 1.e+02 1.e+03 1.e+04 frequency(hz) gain(db) spl=0 spl=1 -60 -50 -40 -30 -20 -10 0 10 20 1.e+02 1.e+03 1.e+04 frequency(hz) gain(db)
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 12 - ? audio path frequency response (emphasis:on) figure 3: tx overall response with pre-emphasis. figure 4: rx overall response with de-emphasis. -60 -50 -40 -30 -20 -10 0 10 20 1.e+02 1.e+03 1.e+04 frequency(hz) gain(db) spl=0 spl=1 -60 -50 -40 -30 -20 -10 0 10 20 1.e+02 1.e+03 1.e+04 frequency(hz) gain(db)
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 13 - 4) scrambler characteristics (scrambler: on , emphasis: off, compandor: off) parameter condition min. typ. max. units notes carrier frequency 3.388 khz modulated output level txino to mod, rxino to rxaf input level 1.0khz -10dbx measuring-freq. 2.388khz -12 -10 -8 dbx high frequency rejection level txino to mod, rxino to rxaf input level 1.0khz -10dbx measuring-freq. 4.388khz -50 dbx carrier signal leakage level txino to mod, rxino to rxaf input level no signal measuring-freq. 3.388khz -50 dbx original signal leakage level txino to mod, rxino to rxaf input level 1.0khz -10dbx measuring-freq. 1.0khz -50 dbx 5) msk modem characteristics parameter condition min. typ. max. units notes tx signal level @mod 1.2khz signal out -12 -11 -10 dbx tx signal distortion @mod 1.2khz signal out -32 db rx signal level @rxino 1.2khz signal out -17 -11 -1 dbx
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 14 - 12. level diagram 1) tx audio system : txrx =0 2) rx audio system : txrx =1 ?dbx? is standardized unit for 1.9v to 5.5v oper ation, 0dbx=-5+20log(vdd/2)dbm, 0dbm=0.775vrms. smf limitter splatter +vr2 txa1 vr1 compressor pre-emphasis txhpf msk modulator scrm /descrm 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 txino +4. 5 -6. 0 db 0 +3.0 -9.2 db 0 crosspoint -10dbx 0db 0db -7.6dbx extlmin 0 -10 -44 -50 -30 -27 -16 -5.5 -5 -10 -11 -7.0 -19.2 -11dbx (msk) -10dbx (audio) dbx txin mod g = 30db -27dbx -30dbx 0db 0db f=1khz rxa2 expander rxa1 vr3 rxlpf de-emphasis rxhpf scrm /descrm 1 0 0 -1 0 -2 0 -2 5 -3 0 -4 0 -4 5 -5 0 -6 0 rxino +3. 5 -4. 0 db 0 +4.5 -18.0 db 0 crosspoint -10dbx -5db -5db +5db expout -5 -10 -25 -30 -25 -20 -14 -6.5 -5 0 -10 -5.5 -28 0dbx (max.) -10dbx (typ.) dbx rxin rxaf vr4 g = 20db 0db rxlpfo g = 0db -40dbx -50dbx -50 -40 f=1khz
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 15 - 13. serial interface configuration 1) register configuration address data a2 a1 a0 function d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 control register 1 bs3 bs2 bs1 txrx txsw2 txsw1 rxsw fsl 0 0 1 control register 2 - - tc em pcont spl msksl fcln 0 1 0 volume register 1 - - - - - vr12 vr11 vr10 0 1 1 volume register 2 - - vr25 vr24 vr23 vr22 vr21 vr20 1 0 0 volume register 3 - vr33 vr32 vr31 vr30 vr42 vr41 vr40 1 0 1 modem register 1 lower 8 bit of modem flame pattern 1 1 0 modem register 2 upper 8 bit of modem flame pattern 1 1 1 test register tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 - - - modem register 3 modem receive data 2) register map 2.1) control register 1 address data a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 bs3 bs2 bs1 txrx txsw2 txsw1 rxsw fsl reset 0 0 0 1 1 1 1 1 2.1.1) operation mode setting bs3 bs2 bs1 mode osc, agnd tx, rx, audio modem 0 0 0 mode0 off off off 0 0 1 mode1 on off off 0 1 0 mode2 on on off 0 1 1 mode3 on off on 1 0/1 0/1 mode4 on on on 2.1.2) tx, rx setting operation data function 0 1 notes txrx tx, rx switch tx operation note 1 rx operation note 2 note 3 rxsw rx audio mute active note 4 fsl rdf/fd switch fd enable rdf enable 2.1.3) tx audio path setting txsw2 txsw1 operation notes 0 0 external tone operation (extlimin --- limiter --- splatter) 0 1 modem operation (msk modulator --- splatter) 1 0 audio operation (hpf --- limiter --- splatter) 1 1 mute (agnd --- limiter --- splatter)
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 16 - note 1: txin to expout path is available by setting txrx=0 and rxsw=1 in register. however, scrambler/descrambler circuit does not work properly on this setting, so please set pcont=1 (disable). to set rxsw=0 makes expout pin mute in operation. note 2: rxin to mod path is available by setting txrx=1 and txsw2/txsw1=1/0 in register. however, scrambler/descrambler circuit does not work properly on this setting, so please set pcont=1 (disable). to set txsw2/txsw1=1/1 makes mod pin mute in operation. note 3: please set a gain level properly in each circuit block according to level diagram in page 14. note 4: rxlpfo pin does not be controlled by setting rxsw=0. it is normally active in rx mode. 2.2) control register 2 address data a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 0 1 - - tc em pcont spl msksl fcln reset - - 1 1 1 1 0 0 operation data function 0 1 notes tc compandor off (disable) on (enable) spl splatter cut-off frequency 2.55khz 3.0khz msksl modem data rate 2400bps 1200bps fcln modem flame detect on (enable) off (disable) em pcont operation notes 1 1 emphasis : on (enable) scrambler : off(disable) 0 1 emphasis : off(disable) scrambler : off(disable) 0/1 0 emphasis : off(disable) scrambler : on (enable) 2.3) volume register 1 address data a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 - - - - - vr12 vr11 vr10 reset - - - - - 1 0 0 vr12 vr11 vr10 vr1 gain (db) 0 0 0 -6.0 0 0 1 -4.5 0 1 0 -3.0 0 1 1 -1.5 1 0 0 0.0 1 0 1 +1.5 1 1 0 +3.0 1 1 1 +4.5
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 17 - 2.4) volume register 2 address data a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 0 1 1 - - vr25 vr24 vr23 vr22 vr21 vr20 reset - - 1 1 0 0 0 0 vr25 vr2 gain (db) 0 -6.0 1 0.0 vr24 vr23 vr22 vr21 vr20 vr2 gain (db) 0 0 0 0 0 -3.2 0 0 0 0 1 -3.0 0 0 0 1 0 -2.8 0 0 0 1 1 -2.6 0 0 1 0 0 -2.4 0 0 1 0 1 -2.2 0 0 1 1 0 -2.0 0 0 1 1 1 -1.8 0 1 0 0 0 -1.6 0 1 0 0 1 -1.4 0 1 0 1 0 -1.2 0 1 0 1 1 -1.0 0 1 1 0 0 -0.8 0 1 1 0 1 -0.6 0 1 1 1 0 -0.4 0 1 1 1 1 -0.2 1 0 0 0 0 0.0 1 0 0 0 1 +0.2 1 0 0 1 0 +0.4 1 0 0 1 1 +0.6 1 0 1 0 0 +0.8 1 0 1 0 1 +1.0 1 0 1 1 0 +1.2 1 0 1 1 1 +1.4 1 1 0 0 0 +1.6 1 1 0 0 1 +1.8 1 1 0 1 0 +2.0 1 1 0 1 1 +2.2 1 1 1 0 0 +2.4 1 1 1 0 1 +2.6 1 1 1 1 0 +2.8 1 1 1 1 1 +3.0
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 18 - 2.5) volume register 3 address data a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 0 - vr33 vr32 vr31 vr30 vr42 vr41 vr40 reset - 1 0 0 0 1 0 0 vr33 vr32 vr31 vr30 vr3 gain (db) 0 0 0 0 -4.0 0 0 0 1 -3.5 0 0 1 0 -3.0 0 0 1 1 -2.5 0 1 0 0 -2.0 0 1 0 1 -1.5 0 1 1 0 -1.0 0 1 1 1 -0.5 1 0 0 0 0.0 1 0 0 1 +0.5 1 0 1 0 +1.0 1 0 1 1 +1.5 1 1 0 0 +2.0 1 1 0 1 +2.5 1 1 1 0 +3.0 1 1 1 1 +3.5 vr42 vr41 vr40 vr4 gain (db) 0 0 0 -18.0 0 0 1 -4.5 0 1 0 -3.0 0 1 1 -1.5 1 0 0 0.0 1 0 1 +1.5 1 1 0 +3.0 1 1 1 +4.5
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 19 - 2.6) modem register 1,2 (reset : low power radio) address data a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 f07 f06 f05 f04 f03 f02 f01 f00 reset 1 0 1 0 1 0 0 0 1 1 0 f15 f14 f13 f12 f11 f10 f09 f08 reset 0 0 0 1 1 0 1 1 2.7) test register address data a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 1 tst7 tst6 tst5 tst4 tst3 tst2 tst1 tst0 reset 1 1 1 1 1 1 1 1 operation data function 0 1 notes tst7..0 test mode test mode normal mode 2.8) modem register 3 address data a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 - - - rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 modem receive data data function 0 1 notes msksl=?0? 2.4khz 1.2khz rd7?0 msksl=?1? 1.8khz 1.2khz rd7 is the first received data.
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 20 - 14. digital ac timing 1) serial interface timing parameter symbol min. typ. max. units master clock frequency fclk 3.6864 mhz clock pulse width 1 clock pulse width 2 ta tb 500 500 ns di/o set up time di/o hold time tc td 100 100 ns dir set up time dir hold time dir falling to sclk falling time te tf tg 100 100 100 ns sclk input rising time sclk input falling time th ti 250 250 ns sclk di/o dir a 2 a 1 a 0 d 1 d 0 tf tg te tb ta 0.8vdd 0.2vdd ti th sclk waveform d 7 tc td
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 21 - 2) msk modulator timing parameter symbol min. typ. max. units txsw2 falling to tclk rising msksl=?0? msksl=?1? t1 208.3 416.7 us tclk period msksl=?0? msksl=?1? t2 416.7 833.3 us txsw2 rising to txsw1 falling t3 2 ms tdata set up time tdata hold time tdata hold time2 ts th th2 1 1 2 us note: the timing of setting the internal registers txsw1 and txsw2 is synchronized with the falling edge of dir pin. 3) msk demodulator timing parameter symbol min. typ. max. units rclk period and fd pulse width msksl=?0? msksl=?1? t 416.7 833.3 us rdf falling to sclk falling time sclk rising to rdf falling time tj tk 100 600 ns tclk txsw 1 tdata th ts t1 t2 txsw 2 audio signal (msksl=?0?) (msksl=?1?) register data th2 t3 mod audio signal
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 22 - rxin rclk rdata fcln rdf/fd rdf/fd sclk di/o dir md 6 md 5 md 4 md 3 md 2 md 1 md 0 md 7 msksl=?0? msksl=?1? t t (internal node) (register data) a b c d rxin rclk rdata fcln rdf/fd rdf/fd sclk di/o dir md 6 md 5 md 4 md 3 md 2 md 1 md 0 md 7 md 7 md 0 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 a2 a1 a0 d7 tk t j d1 d0 d e f g
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 23 - 15. msk modem description 1) msk modulator control flow msk data transmitter, modulator interfaces with tclk, tdata and mod pins and also txrx, txsw2 and txsw1 register as below. (1) setting txrx=0, txsw2=0 and txsw1=1, msk data transmit is provided. (2) a 1200/2400hz clock is put out from tclk pin. synchronizing with the rising edge of tclk, AK2346B reads the msk transmit data from tdata pin and puts out them to mod pin. (3) after transmitting the necessary bit number, please set txsw2=1 (4) afterwards, before switching to audio signal mode, please wait for at least 2ms after setting txsw2=1 to complete sending the msk data final data bit transmit. then set txsw1=1. : msk data transmit compete : switching to audio signal txrx=0 txsw2=0 txsw1=1 y n txsw2=1 waiting 2ms or more txsw1=0 required bit number completed : msk data transmit start : msk data transmitting y msk data are transmitted synchronized to tclk clock
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 24 - 2) msk demodulator control flow msk data receiver, demodulator interfaces wi th rxin, rdf/fd, sclk, di/o and dir pins and also fcln, fsl, and rxsw registers as below. (1) setting fcln=0 and fsl=0 for flame detect mode and also sclk pin sets high level and dir pin sets low level, rdf/fd pin puts out high level and wait for synchronized frame. (point a) (2) after a synchronized frame is detected, rdf/fd pin works as frame detect (fd) mode. fd goes to low level during the period of time ?t?, then fcln is sets to ?1? automatically. (point b, c) (3) monitoring low level of rdf/fd pin, set rxsw=0 for audio signal mute. then set fsl=1 for received flag (rdf), signal put out from rdf/fd pin. (between c and d) : waiting for the next synchronized flame. : having read 8bit data, rdf/fd pin puts out high level. fcln=0 rdf/fd ?low? y n rxsw=0 fsl=1 rdf/fd ?low? reading receive data fcln=0 have all receive data been read out? y : setting for fd signal put out from rdf/fd pin. : synchronized frame pattern detect or not ? : receive audio mute : 8 bit data received or not ? n n y fsl=0 fcln=1 (automatically) : setting flame detect (fd) enable : fd is disable automatically : setting for received flag (rdf) signal put out from rdf/fd pin.
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 25 - (4) after 8 bit received data (md7?0) have been entered to the internal buffer from node rdata, rdf/fd pin goes to low level as rdf mode. (point d) (5) after cpu detects this low level at rdf/fd pin, please puts in 8 clock to sclk pin. then modulated data (rd7?0) put out from di/o pin synchronized with falling edge of sclk clock. (interval e) (6) after 8 clock have been put into sclk pin completely, rdf/fd pin goes to high level that shows all modulated data coming from di/o pin. (point f) (7) by repeating the steps (4), (5), (6), the data come out from di/o pin continuously. (8) after the necessary data have been read, dir pin sets to high level and fcln=0. then internal node rclk and rdata are set to ?1? for initializing and system waits for the next synchronization frame data. (interval g) this frame detection circuit does not have reset function. in case of stopping the sequence during the steps (1) to (8), please set again from the first step (1). especially, when rdf/fd pin goes out low level on frame detecting, fcln register is sets to ?1? automatically as written in (2). if you set fcln=0 during this operation, the date set ?0? is ignored. so please set the data again after rdf/fd pin puts out high level. when frame detection is not used, please set fcln=1 and fsl=1 from the beginning. in that case, monitoring the low level put out from rdf/fd pin, then puts 8 clock into the sclk pin as written in step (4). in this sequence, please program the frame detecting operation by microprocessor.
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 26 - 16. recommended external application circuits 1) txa1 amplifier this is an operational amplifier required for typical transmit microphone. the gain should be less than 30db. to eliminate high frequency noise component over than 100khz from input signal, please compose 1 st or 2 nd order anti-aliasing filter. the following simplified schematic shows an example of 2 nd order anti-aliasing filter that has 30db gain and 10khz cut-off frequency. 2) extlimin pin configuration to eliminate an external dc offset must be decoupled by capacitor to signal input. 3) rxa1 amplifier this is an operational amplifier suitable for receive gain adjuster and anti-aliasing filter to eliminate high frequency noise component over 100khz the gain should be less than 20db. the following simplified schematic shows an example of 2 nd order anti-aliasing filter that has 20db gain and 39khz cut-off frequency. lsi extlimin c c=0.047uf 6 r3 c1=0.47uf r1=10k : _ + lsi c2 r1 rxa1 rxin rxino 22 23 c3 c2=33pf c1 r2 r2=9.1k : r3=100k : c3=560pf agnd r3 c1=0.47uf r1=r2=10k : _ + lsi c2 r1 txa1 txin txino 4 3 c3 c2=33pf c1 r2 r3=330k : c3=2200pf agnd
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 27 - 4) rxa2 amplifier this is an operational amplifier suitable for receive gain adjuster and smoothing filter to eliminate 461khz sampling clock component included in expout pin. the following simplified schematic shows an example of 1 st order low-pass filter that has 0db gain and 19khz cut-off frequency. 5) power supply stabilizing capacitors to connect capacitors between vdd and vss pin reduc e the ripple and noise included in power supply. these capacitors are mounted close to the device pins. 6) agnd, agndin pin stabilizing please decouple to vss level by the 0.3uf or larger capacitor. these capacitors are mounted close to the device pins. agndin lsi c agnd c c=1uf 1 2 expout r1 c1=0.022uf r1=r2=56k : _ + lsi c2 r2 rxa2 18 rxaf rxafin 19 20 c1 c2=150pf lsi c2 vdd vss c1 c1=22uf (electrolytic cap) c2=0.1uf (ceramic cap) vdd vss 17 8
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 28 - 7) clock generation the clock source can be chosen either internally generating with crystal oscillator or externally supplied. figure 1 shows internally generating using the on-chip amplifier, a crystal oscillator, resistor and capacitors. AK2346B is designed to get a stable oscillation for the electrical equivalent circuitry of quartz crystal unit: resonance resistance 150 (max.) and shunt capacitance 5pf(max.). recommended external capacitance is 22pf due not to exceed the load capacitance 16pf (5pf+22pf//22pf). these external components are mounted close to the device pins. figure 2 and 3 show externally supplied example of clock generation. the first gate of xin pin is composed of non-voltage-tracking type amplifier that threshold level is 0.8v. in case the high level of input clock amplitude equals or greater than 1.5v and the low level equals or smaller than 0.5v, recommended configuration is figure 2. in case clock peak-to-peak level equals or greater than 0.2v and equals or smaller than 1.0v, recommended configuration is figure 3. please be careful not to let the clock amplitude exceed the absolute maximum ratings. :w lsi xin 22pf xout 1m 22pf 3.6864mhz figure 1 figure 3 lsi xin 0.01uf xout 1m 3.6864mhz external clock in lsi xin xout 3.6864mhz figure 2 external clock in 16 15
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 29 - 8) limlv pin configuration limlv pin is an adjuster for the limit level of audio signal at baseband. it operates in left open or applying a dc voltage. in case of left open, limit level sets predetermined value depending on the vdd level, which can be calculated using the following formula: hvref = 0.256 x (vdd - agnd) [vo-p] for example at vdd=3v hvref=0.256 x (3.0 - 1.5)=0.384vo-p so typical peak-to-peak limit level is calculated as 1.5 0.384vp-p in case of applying a dc voltage higher than agnd(=1/2vdd) level, the limit level can be adjusted according to following formula: vlimit = agnd (limlv-agnd) for example at vdd=3v, typical limit leve l: vlimit is calculated as below. limlv = 1.6v vlimit = 1.5 0.1v 1.7v 1.5 0.2v 1.8v 1.5 0.3v 1.9v 1.5 0.4v 1.933v 1.5 0.433v (corresponding to ?6.6dbx (max.) ) limiter circuitry operates at agnd level common. in case of applying a dc voltage usage, recommended external configuration is com posed of vdd and agnd level separation with resistors. typical resistor value is r1+r2=51k lsi limlv r1 vdd vss r2 r1+r2 agnd 5
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 30 - 17. packaging ? marking [ contents of ywwlz ] y: last digit of calendar year. (year 2011->1, 2012->2) ww: manufacturing week number. l: lot identification, given to each product lot which is made in a week. lot id is given in alphabetical order (a, b, c?). z: assembly plant code ? 24-pin ssop mechanical outline akm ak2346 ywwlz 8.40 max unit : mm 1 3 24 11 2 0.10 5.9 ma x 0 to 8 0.13 m 0.100.10 2.10 max 0.600.15 7.900.2 0 0.650.08 0.300.10 0.220.05
asahi kasei [AK2346B] ms1409-e-00 2012/05 - 31 - 18. important notice important notice z these products and their s pecifications are subject to change wi thout notice. when you consider any use or ap plication of these products, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and ot her related information contained in this document are provided only to ill ustrate the operation and application examples of the semiconductor products. you are fully responsible for the in corporation of these external circuits, application circuits, software and other related inform ation in the design of your equipments. akm assumes no responsibility for any lo sses incurred by you or third parties arising from the use of these informat ion herein. akm assumes no liabilit y for infringement of any patent, intellectual property, or other rights in the applicati on or use of such inform ation contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the count ry of export pertaining to customs and tariffs, currency ex change, or strategic materials. z akm products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other haz ard related device or system note2) , and akm assumes no responsibility for such use, exc ept for the use approved with t he express written consent by representative director of akm. as used here: note1) a critical component is one whose failu re to function or perform may reasonably be expected to result, whether directly or indirectly , in the loss of the safe ty or effectiveness of the device or system containing it, and which mu st therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nucl ear energy, or other fields, in which its failure to function or perfo rm may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buy er or distributor of akm products, who distributes, di sposes of, or otherwise places the product with a third party, to notify such thir d party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

▲Up To Search▲

Price & Availability of AK2346B

	To Download AK2346B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .